Miniaturization of integrated circuit (IC) packages which may be incorporated in portable consumer products such as cellular phones, and mobile or laptop computers, has become increasingly important. One approach to miniaturization is the use of multi-chip modules where multiple chips having related functions are incorporated in a single package.
Single packages may also include stacked chips, in which chips are vertically stacked on top of each other. A potential drawback to using stacked die techniques is that no interconnection exists on the surfaces of the stacked die; the die interconnect is limited to die-to-die and die-to-substrate interconnections. Therefore, the IC die count is typically limited to one die per attach surface. It is not feasible to attach discrete electronic components to these surfaces since they typically require solderable attachment lands and interconnect circuitry or a noble metal surface for low contact resistance connections.
As such, it would be desirable to improve the manner in which discrete electronic components are incorporated in IC packages, such as utilizing die surfaces not conventionally used for die interconnections.